This rule checks that all input ports are connected. An unconnected port may point out a missing implementation.
With detectPartiallyUnconnected parameter set to false:
entity top is
port (
clk : in std_logic;
i1 : in std_logic;
i2 : in std_logic; -- Noncompliant: Unconnected
i3 : in std_logic_vector(1 downto 0); -- Compliant: Partially connected (bit offset #0)
o1 : out std_logic;
o2 : out std_logic
);
end entity;
architecture rtl of top is begin
process (clk) is
begin
if rising_edge(clk) then
o1 <= i1;
o2 <= i3(0);
end if;
end process;
end architecture;
With detectPartiallyUnconnected parameter set to true:
entity top is
port (
clk : in std_logic;
i1 : in std_logic;
i2 : in std_logic; -- Noncompliant: 'i2' input port is not connected
i3 : in std_logic_vector(1 downto 0); -- Noncompliant: Partially unconnected (bit offset #1)
o1 : out std_logic;
o2 : out std_logic
);
end entity;
architecture rtl of top is begin
process (clk) is
begin
if rising_edge(clk) then
o1 <= i1;
o2 <= i3(0);
end if;
end process;
end architecture;