Why is this an issue?

All the input signals of the top-level module should be registered.

Note that the following input signals are not checked by this rule:

• Clocks
• Unconnected input signals

How to fix it

Code examples

Noncompliant code example

module top (
  input clk, // Not checked: Clock signal
  input a, // Noncompliant: Directly connected to AND cell (o <= a & b)
  input b, // Noncompliant: Directly connected to AND cell (o <= a & b)
  input c, // Not checked: Not connected
  output reg o
);
  always @(posedge clk) begin
    o <= a & b;
  end
endmodule

Compliant solution

module top (
  input clk, // Not checked: Clock signal
  input a, // Compliant
  input b, // Compliant
  input c, // Not checked: Not connected
  output reg o
);
  reg a_reg, b_reg;
  always @(posedge clk) begin
    a_reg <= a;
    b_reg <= b;
    o <= a_reg & b_reg;
  end
endmodule