Why is this an issue?

Whether to use active-high or active-low resets often depends on various factors including design conventions, hardware specifics, and personal or organizational preferences. However, there's a leaning towards preferring active-high resets for several reasons:

1. Consistency with Other Logic
   • Positive Logic: Most logic operations in digital design are based on positive logic where a high signal (1) means true or active, and low (0) means false or inactive. Using an active-high reset aligns with this convention, making the design more intuitive.
   • Uniformity: When all control signals (like enable, set, reset) follow the same convention, it reduces confusion and potential errors in design or verification.
2. Power-Up State:: Many digital systems power up with all pins in a low state due to pull-down resistors or because of how power is applied. An active-high reset ensures that the reset state is not inadvertently entered during power-up or in the absence of a clock signal, assuming the reset signal is driven high when needed.
3. Signal Integrity: In environments where noise is a concern, high signals (active-high) can be less susceptible to noise-induced false resets compared to active-low signals, which might accidentally trigger if noise pulls them low.
4. Design and Verification Ease
   • Simpler Logic: Active-high resets can often lead to simpler logic design because they match the natural flow of many control signals in digital circuits. This might result in fewer inverters or less complex logic for reset conditions.
   • Simulation and Testing: In simulation or verification, active-high resets can make testbenches and assertions easier to write since setting a signal high to reset is more intuitive than pulling it low.
5. Tool Support: Some synthesis tools might optimize designs better with active-high resets, or the logic might synthesize more efficiently. Although modern tools handle both well, there's often a slight edge in optimization for active-high setups.
6. Glitches and Synchronization: For asynchronous resets, an active-high reset might be less likely to cause glitches or timing issues because the reset signal is not naturally in sync with the clock (which typically toggles from low to high), reducing the likelihood of race conditions.

In summary, while there's no one-size-fits-all answer, active-high resets are generally preferred due to alignment with positive logic, better noise immunity, and ease of design and verification. However, the choice should ultimately be guided by the specific requirements of the design, the technology being used, and the overall design philosophy of the team or company.

How to fix it

Code examples

Noncompliant code example

process(clk) is
begin
  if rising_edge(clk) then
    if rst = '0' then -- Noncompliant: Active-low reset
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

process(clk, rst) is
begin
  if rst = '0' then -- Noncompliant: Active-low reset
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Compliant solution

process(clk) is
begin
  if rising_edge(clk) then
    if rst = '1' then -- Compliant: Active-high reset
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

process(clk, rst) is
begin
  if rst = '1' then -- Compliant: Active-high reset
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Resources

Related rules

• Active-low resets should be preferred over active-high resets