Why is this an issue?

While the trend in modern digital design might lean towards active-high resets for many reasons, there are still compelling arguments for preferring active-low resets in certain contexts. Here are some reasons why active-low resets might be preferred:

1. Historical Reasons and Convention
   • Legacy Systems: Many older systems or established design practices use active-low resets. Consistency with existing designs, especially in maintenance or expansion scenarios, can dictate the use of active-low resets.
   • Industry Standards: Certain industries or standards might specify active-low for resets, which could be for historical reasons or due to specific operational requirements.
2. Hardware Implementation
   • Simpler Wiring: In some cases, especially with older technologies or when dealing with external devices, wiring an active-low reset might be simpler or require fewer components like inverters.
   • Pull-Down Resistors: Active-low signals can be easier to implement with pull-down resistors, ensuring a defined state (reset) when no active signal is present, which can be beneficial for power-up scenarios.
3. Power-On Reset: In some systems, especially those where power management is critical, an active-low reset can ensure that the system is reset during power-up or in case of power loss because most signals naturally fall to ground (low) when power is removed or not yet stable.
4. Noise and Glitch Protection
   • Noise Rejection: If the reset line is particularly susceptible to noise, an active-low reset can benefit from the noise margin near ground being potentially larger than near Vcc, making it less likely for noise to inadvertently cause a reset.
   • Glitch Handling: For asynchronous resets, an active-low reset might be less prone to glitches since a momentary noise spike (upwards) on an active-high reset could cause an unintended reset, whereas a spike on an active-low would not unless it pulls the line very close to or at Vcc.
5. Design and Verification
   • Testability: Active-low can sometimes make verification easier if the design environment or test equipment naturally works better with or is set up for active-low signals.
   • Asynchronous Reset: In some design scenarios, an active-low reset might be easier to handle in terms of timing and metastability, especially if the reset needs to be asynchronous to the clock.
6. Fail-Safe: If a system needs to fail in a safe or known state, active-low might be preferred because if the reset line breaks or disconnects, it will naturally go to a low state, thus resetting the system.

In conclusion, while active-high resets are often favored for their alignment with positive logic and ease in many modern designs, active-low resets can be preferred based on specific requirements, historical context, or particular hardware considerations. The choice should reflect the needs of the project, including considerations for reliability, safety, and ease of integration with existing systems or standards.

How to fix it

Code examples

Noncompliant code example

process(clk) is
begin
  if rising_edge(clk) then
    if rst = '1' then -- Noncompliant: Active-high reset
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

process(clk, rst) is
begin
  if rst = '1' then -- Noncompliant: Active-high reset
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Compliant solution

process(clk) is
begin
  if rising_edge(clk) then
    if rst = '0' then -- Compliant: Active-low reset
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

process(clk, rst) is
begin
  if rst = '0' then -- Compliant: Active-low reset
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Resources

Related rules

• Active-high resets should be preferred over active-low resets