Why is this an issue?

While rising edge clocks are more commonly used, there are specific scenarios where a falling edge (negative edge) might be preferred:

1. Power and Noise Considerations:
   • Power Consumption: In some CMOS designs, using a falling edge can lead to lower dynamic power consumption due to reduced short-circuit current during transistor switching.
   • Noise Reduction: The falling edge might be less noisy due to less ground bounce or power supply noise, especially in systems with high simultaneous switching activity on the rising edge.
2. Timing and Skew:
   • Clock Distribution: If there's a predictable skew favoring the falling edge, it might be used for more consistent timing across the chip.
   • Hold Time: In certain designs, hold time constraints might be more easily met with a falling edge clock due to natural alignment with data setup times.
3. Design Symmetry and Simplicity:
   • Symmetrical Design: Using falling edges for symmetry in dual-edge systems or to balance load can be beneficial.
   • Less Common Usage: In multi-domain systems, using falling edges might reduce race conditions or timing conflicts when different domains use opposite edges.
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4. Testing and Debug:
   • Debugging: If debugging tools or methodologies are better suited for falling edge clocks, this might influence the choice.
5. Legacy or Standard Practices:
   • Compatibility: For legacy systems or integration where falling edges are standard, sticking with them ensures compatibility.

Drawbacks of Using Falling Edge Clocks:

• Less Common Support: Most tools and methodologies are designed for rising edge clocks, potentially leading to less support or increased complexity in design and verification.
• Synchronization Issues: Synchronization becomes more complex if the system interacts with predominantly rising edge designs.
• Perception and Convention: There's a strong convention towards rising edge clocks, which might cause confusion or errors if not clearly documented.

In conclusion, while falling edge clocks have their advantages in specific contexts, the choice largely depends on system requirements, power constraints, noise sensitivity, timing, and compatibility. Rising edge clocks remain the norm due to convention, support, and simplicity unless there's a significant reason to opt for falling edges.

How to fix it

Code examples

Noncompliant code example

process(clk) is
begin
  if(clk'event and clk='1') then -- Noncompliant: Rising
    xr <= not xr;
  end if;

  if(not clk'stable and clk='1') then -- Noncompliant: Rising
    xr <= not xr;
  end if;

  if(rising_edge(clk)) then -- Noncompliant: Rising
    xr <= not xr;
  end if;
end process;

Compliant solution

process(clk) is
begin
  if(clk'event and clk='0') then -- Compliant: Falling
    xr <= not xr;
  end if;

  if(not clk'stable and clk='0') then -- Compliant: Falling
    xr <= not xr;
  end if;

  if(falling_edge(clk)) then -- Compliant: Falling
    xr <= not xr;
  end if;
end process;

Resources

Related rules

• Rising should be preferred over rising to detect clock transitions