Why is this an issue?

There should not be any reason to have a latch in your design. It is likely a coding mistake. Thus, all latches should be removed.

How to fix it

Code examples

Noncompliant code examples

entity top is
  port (
    i_A    : in  std_logic;
    i_data : in  std_logic_vector(7 downto 0);
    o_data : out std_logic_vector(7 downto 0)
  );
end;

architecture rtl of top is
  signal data : std_logic_vector(7 downto 0) := (others => '0');
begin
  process(i_A, i_data, data) is -- Latch inferred for 'data'
  begin
    if i_A = '1' then
      data <= i_data;
    else
      data <= data;
    end if;
  end process;
  o_data <= data;
end;

entity top is
  port (
    i_A    : in  std_logic;
    i_data : in  std_logic_vector(7 downto 0);
    o_data : out std_logic_vector(7 downto 0)
  );
end;

architecture rtl of top is
  signal data : std_logic_vector(7 downto 0) := (others => '0');
begin
  data <= i_data when i_A = '0' else data; -- Latch inferred for 'data'
  o_data <= data;
end;

entity top is
  port (
    A, B, C, X : in  integer range 0 to 15;
    Z          : out integer range 0 to 15
  );
end;

architecture rtl of top is
begin
  process (A, B, C, X) is -- 'Z' not assigned for all possible values of X, latch inferred for 'Z'
  begin
    case X is
      when 0 =>
         Z <= A;
      when 7 | 9 =>
         Z <= B;
      when 1 to 5 =>
         Z <= C;
      when others =>
    end case;
  end process;
end;

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