Why is this an issue?

A flip-flop doesn't always need a reset, but including one is often recommended.

• Initialization: A reset ensures the flip-flop starts in a known state (e.g., 0 or 1) when the system powers up or after a specific event. Without a reset, the initial state of a flip-flop is undefined, which can lead to unpredictable behavior in sequential circuits.
• System Stability: In state machines or control logic, an undefined initial state can cause the system to enter an invalid or unintended state, leading to errors or erratic behavior. A reset provides a reliable way to initialize the system to a safe state.
• Simulation and Synthesis: During simulation, flip-flops without a reset may initialize to unknown ('X') states, complicating debugging. In synthesis, some FPGA or ASIC technologies may not guarantee a specific power-on state, so a reset ensures consistency across platforms.
• Error Recovery: A reset allows the system to recover from errors or unexpected conditions by forcing the flip-flop back to a known state, improving robustness.
• Design Reusability: Including a reset makes the design more portable and reusable across different platforms or applications, as many systems expect or require reset functionality.

How to fix it

Code examples

Noncompliant code examples

entity top is
  port (
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic
  );
end top;

architecture rtl of top is
begin
  process (clk)
  begin
    if rising_edge(clk) then -- Noncompliant: No reset
      q <= d;
    end if;
  end process;
end rtl;

Compliant solution

entity top is
  port (
    clk   : in std_logic;
    reset : in std_logic;
    d     : in std_logic;
    q     : out std_logic
  );
end top;

architecture rtl of top is
begin
  process (clk, reset)
  begin
    if reset = '1' then -- Compliant
      q <= '0';
    elsif rising_edge(clk) then
      q <= d;
    end if;
  end process;
end rtl;