Why is this an issue?

Branching preprocessor directives ( `ifdef, `ifndef, `else, `elsif , `endif) should be aligned to the left, even if they are nested. The objective is to easily spot those conditional directives.

How to fix it

Code examples

Noncompliant code example

package my_package;
  `ifdef FOO
    parameter bit ABC = 1;
  `else
    parameter bit ABC = 2;
  `endif
endpackage : my_package

Compliant solution

package my_package;
`ifdef FOO
  parameter bit ABC = 1;
`else
  parameter bit ABC = 2;
`endif
endpackage : my_package

Resources

Articles & blog posts

• lowRISC Verilog Coding Style Guide - Indentation - Preprocessor Directives