Why is this an issue?

Sharing some naming conventions is a key point to make it possible for a team to efficiently collaborate. This rule allows to check that all generate block labels match a provided regular expression.

How to fix it

Code examples

Noncompliant code example

With default regular expression ^(gen_|g_)[a-z0-9_]+$:

for (genvar ii = 0; ii < NumberOfBuses; ii++) begin : my_buses // Noncompliant: 'my_buses' does not comply with naming convention
  my_bus #(.index(ii)) i_my_bus (.foo(foo), .bar(bar[ii]));
end : my_buses

Compliant solution

With default regular expression ^(gen_|g_)[a-z0-9_]+$:

for (genvar ii = 0; ii < NumberOfBuses; ii++) begin : gen_my_buses
  my_bus #(.index(ii)) i_my_bus (.foo(foo), .bar(bar[ii]));
end : gen_my_buses

Resources

Articles & blog posts

• lowRISC Verilog Coding Style Guide - Naming

Related rules

• "generate" blocks should be labelled
• "generate" blocks should repeat their label at the end of the block
• "generate" block label should be placed right before the "begin" keyword
• "generate" block label should be placed right after the "begin" keyword