Why is this an issue?

To be able to embed Verilog/SystemVerilog code into VHDL code, this rule checks if VHDL reserved words are used as:

Module name
Port name
Parameter name

The following keywords are checked:

abs, access, after, alias, all, and, architecture, array, assert, assume, assume_guarantee, attribute, begin, block, body, buffer, bus, case, component, configuration, constant, context, cover, default, disconnect, downto, else, elsif, end, entity, exit, fairness, file, for, force, function, generate, generic, group, guarded, if, impure, in, inertial, inout, is, label, library, linkage, literal, loop, map, mod, nand, new, next, nor, not, null, of, on, open, or, others, out, package, parameter, port, postponed, procedure, process, property, protected, pure, range, record, register, reject, release, rem, report, restrict, restrict_guarantee, return, rol, ror, select, sequence, severity, shared, signal, sla, sra, srl, strong, subtype, then, to, transport, type, unaffected, units, until, use, variable, vmode, vprop, vunit, wait, when, while, with, xnor, xor,

How to fix it

Code examples

Noncompliant code example

module entity; // Noncompliant: "entity" is a VHDL reserved keyword
  ...
endmodule

Compliant solution

module fly;
  ...
endmodule