More than one specify timing path was given for a particular pair of input and output terminals in a
module.
Duplicated timing paths should be removed.
module fly(input a, output b);
specify
(a => b) = 1;
(a => b) = 2; // Noncompliant
endspecify
endmodule
module fly(input a, output b);
specify
(a => b) = 1;
endspecify
endmodule