Why is this an issue?

SystemVerilog always_comb or always_ff or always_latch should be used instead of Verilog always.

How to fix it

Code examples

Noncompliant code example

module top;
  logic a, b, c;
  always @(*) begin
    c = a + b;
  end
endmodule

Compliant solution

module top;
  logic a, b, c;
  always_comb begin
    c = a + b;
  end
endmodule

Resources

Articles & blog posts

• lowRISC Verilog Coding Style Guide - Appendix - Condensed Style Guide - Language features

• SystemVerilog always_comb, always_ff. New and Improved