Why is this an issue?

An implicit named port connection is made between two inequivalent types. Unlike with a normal port connection, where the type of the connection undergoes implicit conversion, the SystemVerilog standard specifies that this case is an error.

Even if some tools support this syntax, you should refrain from using it to keep your code portable.

How to fix it

Code examples

Noncompliant code example

module fly(logic p);
endmodule

module dream;
  int p;
  fly fly1(.p);
endmodule