Why is this an issue?

A pulsestyle or showcancelled declaration targets an output terminal that has previously been used in a timing path declaration, which is not allowed according to the SystemVerilog standard.

How to fix it

Code examples

Noncompliant code example

module m(input a, output b);
  specify
    (a => b) = 1;
    pulsestyle_ondetect b; // Noncompliant
  endspecify
endmodule