Why is this an issue?

[[sharing_naming_conventions]] This rule allows to check that all port names match a provided regular expression. Different naming conventions can be defined for input, output, inout and ref ports.

This rule checks ANSI ports.

How to fix it

Code examples

Noncompliant code example

With default regular expression for input ports ^[a-z]_i|[a-z]+[a-z0-9_]*[a-z0-9]+_i$:

module (input MyInput);
endmodule

Compliant solution

With default regular expression for input ports ^[a-z]_i|[a-z]+[a-z0-9_]*[a-z0-9]+_i$:

module (input my_input);
endmodule

Resources

Articles & blog posts

• lowRISC Verilog Coding Style Guide - Naming