Why is this an issue?

Two entities with the same name cannot be synthesized/simulated for a same FPGA target project.

How to fix it

Code examples

Noncompliant code example

File 1:
entity fly is
  ...
end;

File 2:
entity fly is
  ...
end;

Compliant solution

File 1:
entity fly is
  ...
end;

File 2:
entity dream is
  ...
end;