Why is this an issue?

Setting default value to signal in declaration section is usually not synthesizable and, thus, should be avoided in synthesis files.

How to fix it

Code examples

Noncompliant code example

architecture my_architecture of my_entity is
  signal my_signal_1 : std_logic := '0'; -- NonCompliant
begin
end;

Compliant solution

With default allowSignalInitializationThroughFunction parameter value: false

architecture my_architecture of my_entity is
  signal my_signal : std_logic;
begin
  my_signal := '0';
end;

With allowSignalInitializationThroughFunction parameter value set to true

architecture my_architecture of my_entity is
  signal my_signal : std_logic_vector(7 to 0) := init(kbits);
begin
end;