Why is this an issue?

When the number of actual states of the FSM does not match the number of states defined in its type, it means that some states listed in the type are not implemented in the FSM.

How to fix it

Code examples

Noncompliant code example

entity fsm is
  port (
    clk : in std_logic;
    rst : in std_logic;
    data_in : in std_logic;
    data_out : out std_logic_vector(2 downto 0)
  );
end;

architecture rtl of fsm is
  type fsm_type is (S0, S1, S2, S3, S4); -- Noncompliant: S4 is unreachable
  signal state : fsm_type;
begin
  process(clk, rst)
  begin
    if rst = '1' then
      state <= S0;
    elsif rising_edge(clk) then
      case state is
        when S0 =>
          if data_in = '1' then
            state <= S1;
          else
            state <= S2;
          end if;
        when S1 =>
          if data_in = '1' then
            state <= S2;
          else
            state <= S3;
          end if;
        when S2 =>
          if data_in = '1' then
            state <= S3;
          else
            state <= S2;
          end if;
        when S3 =>
          if data_in = '1' then
            state <= S0;
          else
            state <= S2;
          end if;
        when S4 =>
          if data_in = '1' then
            state <= S0;
          else
            state <= S1;
          end if;
      end case;
    end if;
  end process;

  process(state)
  begin
    case state is
      when S0 =>
        data_out <= "000";
      when S1 =>
        data_out <= "010";
      when S2 =>
        data_out <= "100";
      when S3 =>
        data_out <= "110";
      when S4 =>
        data_out <= "111";
    end case;
  end process;
end;

Compliant solution

entity fsm is
  port (
    clk : in std_logic;
    rst : in std_logic;
    data_in : in std_logic;
    data_out : out std_logic_vector(2 downto 0)
  );
end;

architecture rtl of fsm is
  type fsm_type is (S0, S1, S2, S3, S4);
  signal state : fsm_type;
begin
  process(clk, rst)
  begin
    if rst = '1' then
      state <= S0;
    elsif rising_edge(clk) then
      case state is
        when S0 =>
          if data_in = '1' then
            state <= S1;
          else
            state <= S2;
          end if;
        when S1 =>
          if data_in = '1' then
            state <= S2;
          else
            state <= S3;
          end if;
        when S2 =>
          if data_in = '1' then
            state <= S3;
          else
            state <= S4;
          end if;
        when S3 =>
          if data_in = '1' then
            state <= S0;
          else
            state <= S2;
          end if;
        when S4 =>
          if data_in = '1' then
            state <= S0;
          else
            state <= S1;
          end if;
      end case;
    end if;
  end process;

  process(state)
  begin
    case state is
      when S0 =>
        data_out <= "000";
      when S1 =>
        data_out <= "010";
      when S2 =>
        data_out <= "100";
      when S3 =>
        data_out <= "110";
      when S4 =>
        data_out <= "111";
    end case;
  end process;
end;