To better understand reset usage, reset names should be preserved across the design.
With prefixToIgnore and suffixToIgnore parameters not set:
entity top is
port(
rst : in std_logic;
...
)
end;
entity fly is
port(
i_myreset : in std_logic; -- Noncompliant: 'i_myreset' should be 'rst' instead
...
)
end;
architecture rtl of top is
begin
fly_i1 : entity work.fly(rtl)
port map(
i_myreset => rst, -- Noncompliant: 'i_myreset' should be 'rst' instead
...
);
end;
With prefixToIgnore set to (i|o|io)_:
entity top is
port(
rst : in std_logic;
...
)
end;
entity fly is
port(
i_myreset : in std_logic; -- Noncompliant: 'i_myreset' should be either 'rst' or 'i_rst'
...
)
end;
architecture rtl of top is
begin
fly_i1 : entity work.fly(rtl)
port map(
i_myreset => rst, -- Noncompliant: 'i_myreset' should be either 'rst' or 'i_rst'
...
);
end;
With prefixToIgnore and suffixToIgnore parameters not set:
entity top is
port(
rst : in std_logic;
...
)
end;
entity fly is
port(
rst : in std_logic; -- Compliant
...
)
end;
architecture rtl of top is
begin
fly_i1 : entity work.fly(rtl)
port map(
rst => rst, -- Compliant
...
);
end;
With prefixToIgnore set to (i|o|io)_:
entity top is
port(
rst : in std_logic;
...
)
end;
entity fly is
port(
i_rst : in std_logic; -- Compliant
...
)
end;
architecture rtl of top is
begin
fly_i1 : entity work.fly(rtl)
port map(
i_rst => rst, -- Compliant
...
);
end;