Why is this an issue?

To improve portability and changeability, clock signal names should not contain any frequency information. An issue is raised when a clock signal name contains some digits.

How to fix it

Code examples

Noncompliant code example

entity top is
  port(
    clk10MHz : in std_logic;
    ...
  );
end;

Compliant solution

entity top is
  port(
    clk_fly : in std_logic;
    ...
  );
end;