All references should have the same case as the corresponding declarations. This is a convention rule since VHDL is not case-sensitive.
procedure proc is variable tmp : std_ulogic := '0'; constant cst : std_ulogic := '0'; begin tmp <= Cst; -- Noncompliant: Wrong case for identifier "Cst". Should be "cst" instead. end PROC; -- Noncompliant: Wrong case for identifier "PROC". Should be "proc" instead.
procedure proc is variable tmp : std_ulogic := '0'; constant cst : std_ulogic := '0'; begin tmp <= cst; end proc;