Why is this an issue?

Sharing some naming conventions is a key point to make it possible for a team to efficiently collaborate. This rule allows to check that all file names match a provided regular expression. Different regular expressions can be provided for synthesis and simulation files.

Also, a specific pattern can be added to the regular expression to check that the file name contains the name of the entity defined within this file. If the file contains several entities (that is not recommended), the pattern will be checked against the name of the first entity defined in the file.

How to fix it

Code examples

Noncompliant code example

With default regular expression for synthesis file: ^[a-zA-Z][a-zA-Z0-9_]*\.(vhd|vhdl)$

File name: my-file.vhd (- is not allowed in file name)

With custom regular expression for synthesis file: ^{DESIGN_UNIT}[a-zA-Z0-9_]*.vhd$

entity my_first_entity is -- Noncompliant: File name does not start with entity name
  port(a : in std_logic);
end;

Compliant solution

With default regular expression for synthesis file: ^[a-zA-Z][a-zA-Z0-9_]*\.(vhd|vhdl)$

File name: my_file.vhd

With custom regular expression for synthesis file: ^{DESIGN_UNIT}[a-zA-Z0-9_]*.vhd$

entity my_entity is -- Compliant: File name starts with entity name
  port(a : in std_logic);
end;