Why is this an issue?

Only synthesizable types should be used in design:

bit
bit_vector
integer
natural
positive
signed
std_logic
std_logic_vector
std_ulogic
std_ulogic_vector
unsigned

array of those types and record of those types.

Additional types are allowed for generics:

boolean

Note that the list of allowed types can be customized through parameters.

How to fix it

Code examples

Noncompliant code example

With the default values of allowed types: integer,signed,std_logic,std_logic_vector,unsigned

architecture a of e is
  signal s : bit; -- Noncompliant
  constant c : bit; -- Noncompliant

  type my_record_type is record
    a : bit;
    b : std_logic;
  end record;
  signal r : my_record_type; -- Noncompliant: See above record has 'bit' type

  type my_array_type is array(3 downto 0) of bit;
  signal a : my_array_type; -- Noncompliant: See above array type of 'bit'

begin
  process is
    variable v : bit; -- Noncompliant
  begin
  end process;
end;

Compliant solution

With the default values of allowed types: integer,signed,std_logic,std_logic_vector,unsigned

architecture a of e is
  signal s : std_logic;
  constant c : std_logic;

  type my_record_type is record
    a : std_logic;
    b : std_logic;
  end record;

  signal r : my_record_type;

  type my_array_type is array(3 downto 0) of std_logic;
  signal a : my_array_type;

begin
  process is
    variable v : std_logic;
  begin
  end process;
end;